As semiconductor design and manufacturing techniques have improved over time, the degree of integration that can be achieved in semiconductor devices has increased dramatically. With this substantial increase in the degree of device integration, the size of semiconductor memory devices has been sharply reduced while simultaneously achieving significant increases in memory capacity. Generally speaking, the level of integration of a semiconductor device may be increased by reducing the dimensions of at least one, and preferably many, of its constituent parts. Capacitors are included in numerous semiconductor devices such as, for example, semiconductor memory devices. In many instances, such capacitors may have relatively high capacitance levels to, for example, improve device reliability. As such, techniques for forming small, relatively high capacitance capacitors on semiconductor substrates is of interest.
Generally speaking, the capacitance of a capacitor is proportional to the surface dimensions of the capacitor electrode and the dielectric constant of a dielectric layer, and is inversely proportional to the thickness of the dielectric layer. As such, the capacitance of a capacitor may be increased by (1) using a higher dielectric constant material as the dielectric layer, (2) decreasing the thickness of the dielectric layer and/or (3) increasing the surface dimensions of the capacitor electrode. In the last of the above-listed techniques, the surface dimensions of the electrode may be increased by using a cylindrically-shaped structure or a capacitor over bitline (“COB”) structure instead of a planar structure.
As shown in FIG. 1, a COB structure includes a bit line 22 and capacitors 30 that include storage nodes 26, dielectric layers 28 and common electrode 29. The bit line 22 is formed on a semiconductor substrate 10 that includes an active region 13 which is defined by an isolation layer 12. The capacitors 30 include storage nodes 26 and dielectric layers 28, and are formed on the bit line 22 that is between insulation layers 16 and 17. The COB structure formed on the bit line 22 can increase the capacitance achieved for a given cell dimension.
As is also shown in FIG. 1, a first self-aligned contact pad 18a and a second self-aligned contact pads 18b are formed between gate structures of cell transistors 14. The first self-aligned contact pad 18a and the second self-aligned contact pad 18b may be formed, for example, of polysilicon. The first self-aligned contact pad 18a is electrically connected to a first impurity doped (source/drain) region 15a, and the second self-aligned contact pads 18b are each electrically connected to second impurity doped (source/drain) regions 15b. The first impurity doped region 15a is also electrically connected to the bit line 22, and the second impurity doped areas 15b are electrically connected to respective capacitors 30. The electrical connections may include a direct contact 20 and a buried contact 24.
Semiconductor device test patterns may be used to measure operational properties of a semiconductor device. By way of example, to measure operational properties of a cell transistor in, for example, a DRAM memory device, the bit line 22 and the storage node 26, each of which is electrically connected to respective impurity doped areas 15a/15b of the cell transistor 14, may be connected to a probing pad. To accomplish this, the bit line may itself be connected to the probing pad. However, the dielectric layer 28 that is formed on the storage node 26 is an insulation material that reduces, minimizes and/or prevents the flow of electric current. Accordingly, it can prove difficult to connect the storage node 26 to the probing pad. For example, as shown in FIGS. 1-2, a buried contact 24 may be provided that connects the storage node 26 to the impurity doped area 15b. However, in such a design bridging may occur between the buried contact 24 and the direct contact 20 which may reduce the ability to accurately measure leakage current of the cell transistor.
As shown in FIG. 3, conventionally, junction leakage current from a cell transistor and gate induced drain leakage (“GIDL”) has been measured by connecting a probe to any one of the impurity doped regions area in a row of impurity doped regions. As shown in the depiction in FIG. 4 of the layout of a cell transistor array, the leakage of current may also be measured using a semiconductor device test pattern that comprises a probing pad 40 connected to a plurality of buried contacts 20 arranged in parallel rows, as disclosed in Y. P. Kim, IRPS 2001, p. 1 and K. Saino, IEDM 2000, p. 837.